Next: Introduction [Contents][Index]
Next: Building Vericert, Previous: Vericert Manual, Up: Vericert Manual [Contents][Index]
Vericert translates C code into a hardware description language called Verilog, which can then be synthesised into hardware, to be placed onto a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC).
Figure 1.1: Current design of Vericert, where HTL is an intermediate language representing a finite state machine with data-path (FSMD) and Verilog is the target language.
The design shown in Figure Figure 1.1 shows how Vericert leverages an existing verified C compiler called CompCert to perform this translation.
Copyright (C) 2019-2022 Yann Herklotz.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled “GNU Free Documentation License”.
Next: Using Vericert, Previous: Introduction, Up: Vericert Manual [Contents][Index]
To build Vericert, the provided Makefile can be used. External dependencies are needed to build the project, which can be pulled in automatically with nix using the provided default.nix and shell.nix files.
The project is written in Coq, a theorem prover, which is extracted to OCaml so that it can then be compiled and executed. The dependencies of this project are the following:
These dependencies can be installed manually, or automatically through Nix.
Next: Setting up Nix, Up: Building Vericert [Contents][Index]
CompCert is added as a submodule in the ‘lib/CompCert’ directory. It is needed to run the build process below, as it is the one dependency that is not downloaded by nix, and has to be downloaded together with the repository. To clone CompCert together with this project, and check it out at the correct revision, you can run:
git clone -b v1.2.2 --recursive https://github.com/ymherklotz/vericert
If the repository is already cloned, you can run the following command to make sure that CompCert is also downloaded and the correct branch is checked out:
git checkout v1.2.2 git submodule update --init
Next: Makefile build, Previous: Downloading Vericert and CompCert, Up: Building Vericert [Contents][Index]
Nix is a package manager that can create an isolated environment so that the builds are reproducible. Once nix is installed, it can be used in the following way.
To open a shell which includes all the necessary dependencies, one can use:
nix-shell
which will open a shell that has all the dependencies loaded.
Next: Testing, Previous: Setting up Nix, Up: Building Vericert [Contents][Index]
If the dependencies were installed manually, or if one is in the ‘nix-shell’, the project can be built by running:
make -j8
and installed locally, or under the ‘PREFIX’ location using:
make install
Which will install the binary in ‘./bin/vericert’ by default. However, this can be changed by changing the ‘PREFIX’ environment variable, in which case the binary will be installed in ‘$PREFIX/bin/vericert’.
Previous: Makefile build, Up: Building Vericert [Contents][Index]
To test out vericert
you can try the following examples which are in the test folder using the
following:
./bin/vericert test/loop.c -o loop.v ./bin/vericert test/conditional.c -o conditional.v ./bin/vericert test/add.c -o add.v
Or by running the test suite using the following command:
make test
Next: Unreleased Features, Previous: Building Vericert, Up: Vericert Manual [Contents][Index]
Vericert can be used to translate a subset of C into Verilog. As a simple example, consider the
following C file (main.c
):
void matrix_multiply(int first[2][2], int second[2][2], int multiply[2][2]) { int sum = 0; for (int c = 0; c < 2; c++) { for (int d = 0; d < 2; d++) { for (int k = 0; k < 2; k++) { sum = sum + first[c][k]*second[k][d]; } multiply[c][d] = sum; sum = 0; } } } int main() { int f[2][2] = {{1, 2}, {3, 4}}; int s[2][2] = {{5, 6}, {7, 8}}; int m[2][2] = {{0, 0}, {0, 0}}; matrix_multiply(f, s, m); return m[1][1]; }
It can be compiled using the following command, assuming that vericert is somewhere on the path.
vericert main.c -o main.v
The Verilog file contains a top-level test-bench, which can be given to any Verilog simulator to simulate the hardware, which should give the same result as executing the C code. Using Icarus Verilog as an example:
iverilog -o main_v main.v
When executing, it should therefore print the following:
$ ./main_v finished: 50
This gives the same result as executing the C in the following way:
$ gcc -o main_c main.c $ ./main_c $ echo $? 50
Up: Using Vericert [Contents][Index]
vericert - A formally verified high-level synthesis tool.
Next: DESCRIPTION, Previous: NAME, Up: Man pages [Contents][Index]
vericert [ OPTION ]… [ FILE ]…
Do not use HLS and generate standard flow
Simulate the result with the Verilog semantics
Add debug logic to the Verilog
initialise the stack to all 0s
Schedule the resulting hardware [off]
If-conversion optimisation [off]
Set the path of the Compcert run-time library
Print external commands before invoking them
Show the time spent in various compiler passes
Print the version string and exit
Generate code for the given target
Read configuration from file
Read command line options from <file>
Save C file after preprocessing in <file>.i
Save C file after parsing and elaboration in <file>.parsed.c
Save generated C in <file>.compcert.c
Save generated Clight in <file>.light.c
Save generated Cminor in <file>.cm
Save RTL at various optimization points in <file>.rtl.<n>
Save RTLBlock <file>.rtlblock
Save HTL before Verilog generation <file>.htl
Save LTL after register allocation in <file>.ltl
Save generated Mach code in <file>.mach
Save generated assembly in <file>.s
Save all generated intermediate files in <file>.<ext>
Save info for post-linking validation in <file>.json
Generate output in <file>
Enable all warnings
Enable the specific <warning>
Disable the specific <warning>
Make all warnings into errors
Turn <warning> into an error
Turn <warning> into a warning even if -Werror is specified
Turn all errors into fatal errors aborting the compilation
Turn on colored diagnostics
Turn of colored diagnostics
Maximum number of errors to report
Print the option name with mappable diagnostics
Turn of printing of options with mappable diagnostics
Next: COPYRIGHT, Previous: DESCRIPTION, Up: Man pages [Contents][Index]
Written by Yann Herklotz, Michalis Pardalos, James Pollard, Nadesh Ramanathan and John Wickerson.
Copyright (C) 2019-2022 Yann Herklotz <[email protected]>
This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License along with this program. If not, see https://www.gnu.org/licenses/.
Next: Coq Style Guide, Previous: Using Vericert, Up: Vericert Manual [Contents][Index]
The following are unreleased features in Vericert that are currently being worked on and have not been completely proven correct yet. Currently this includes features such as:
This page gives some preliminary information on how the features are implemented and how the proofs for the features are being done. Once these features are properly implemented, they will be added to the proper documentation.
Next: Operation Chaining, Up: Unreleased Features [Contents][Index]
Scheduling is an optimisation which is used to run various instructions in parallel that are independent to each other.
Next: If-conversion, Previous: Scheduling, Up: Unreleased Features [Contents][Index]
Operation chaining is an optimisation that can be added on to scheduling and allows for the sequential execution of instructions in a clock cycle, while executing other instructions in parallel in the same clock cycle.
Next: Functions, Previous: Operation Chaining, Up: Unreleased Features [Contents][Index]
If-conversion is an optimisation which can turn code with simple control flow into a single block (called a hyper-block), using predicated instructions.
Previous: If-conversion, Up: Unreleased Features [Contents][Index]
Functions are currently only inlined in Vericert, however, we are working on a proper interface to integrate function calls into the hardware.
Next: Index - Features, Previous: Unreleased Features, Up: Vericert Manual [Contents][Index]
This style guide was taken from Silveroak, it outlines code style for Coq code in this repository. There are certainly other valid strategies and opinions on Coq code style; this is laid out purely in the name of consistency. For a visual example of the style, see the example at the bottom of this file.
Next: Formatting, Up: Coq Style Guide [Contents][Index]
Next: Import statements, Up: Code organization [Contents][Index]
Next: Notations and scopes, Previous: Legal banner, Up: Code organization [Contents][Index]
Previous: Import statements, Up: Code organization [Contents][Index]
Next: Definitions and Fixpoints, Previous: Code organization, Up: Coq Style Guide [Contents][Index]
Next: Whitespace and indentation, Up: Formatting [Contents][Index]
Previous: Line length, Up: Formatting [Contents][Index]
(Z.pow 1 2) (Z.pow 1 2 3 4 5 6)
Inductive Foo : Type := | FooA : Foo | FooB : Foo .
match x with | 3 => true | _ => false end. lazymatch x with | 3 => idtac | _ => fail "Not equal to 3:" x end. repeat match goal with | _ => progress subst | _ => reflexivity end. do 2 lazymatch goal with | |- context [eq] => idtac end.
Next: Inductives, Previous: Formatting, Up: Coq Style Guide [Contents][Index]
Definition x := 5
instead of Definition x : nat := 5
) when the type is very simple or obvious (for instance, the
definition is in a file which deals exclusively with operations on ‘Z’).
Next: Lemma/Theorem statements, Previous: Definitions and Fixpoints, Up: Coq Style Guide [Contents][Index]
Inductive Foo : Type := | FooA : Foo | FooB : Foo . Inductive Foo : Type := | FooA : Foo | FooB : Foo.
Next: Proofs and tactics, Previous: Inductives, Up: Coq Style Guide [Contents][Index]
Next: Naming, Previous: Lemma/Theorem statements, Up: Coq Style Guide [Contents][Index]
Ltac crush_step := match goal with | _ => progress subst | _ => reflexivity end. Ltac crush := repeat crush_step.
Next: Example, Previous: Proofs and tactics, Up: Coq Style Guide [Contents][Index]
Previous: Naming, Up: Coq Style Guide [Contents][Index]
A small standalone Coq file that exhibits many of the style points.
(* * Vericert: Verified high-level synthesis. * Copyright (C) 2021 Name <[email protected]> * * <License...> *) Require Import Coq.Lists.List. Require Import Coq.micromega.Lia. Require Import Coq.ZArith.ZArith. Import ListNotations. Local Open Scope Z_scope. (* Helper proofs about standard library integers (Z) go within [Module Z] so that they match standard-library Z lemmas when used. *) Module Z. Lemma pow_3_r x : x ^ 3 = x * x * x. Proof. lia. Qed. (* very short proofs can go all on one line *) Lemma pow_4_r x : x ^ 4 = x * x * x * x. Proof. change 4 with (Z.succ (Z.succ (Z.succ (Z.succ 0)))). repeat match goal with | _ => rewrite Z.pow_1_r | _ => rewrite Z.pow_succ_r by lia | |- context [x * (?a * ?b)] => replace (x * (a * b)) with (a * b * x) by lia | _ => reflexivity end. Qed. End Z. (* Now we can access the lemmas above as Z.pow_3_r and Z.pow_4_r, as if they were in the ZArith library! *) Definition bar (x y : Z) := x ^ (y + 1). (* example with a painfully manual proof to show case formatting *) Lemma bar_upper_bound : forall x y a, 0 <= x <= a -> 0 <= y -> 0 <= bar x y <= a ^ (y + 1). Proof. (* avoid referencing autogenerated names by explicitly naming variables *) intros x y a Hx Hy. revert y Hy x a Hx. (* explicitly indicate # subgoals with [ | ... | ] if > 1 *) cbv [bar]; refine (natlike_ind _ _ _); [ | ]. { (* y = 0 *) intros; lia. } { (* y = Z.succ _ *) intros. rewrite Z.add_succ_l, Z.pow_succ_r by lia. split. { (* 0 <= bar x y *) apply Z.mul_nonneg_nonneg; [ lia | ]. apply Z.pow_nonneg; lia. } { (* bar x y < a ^ y *) rewrite Z.pow_succ_r by lia. apply Z.mul_le_mono_nonneg; try lia; [ apply Z.pow_nonneg; lia | ]. (* For more flexible proofs, use match statements to find hypotheses rather than referring to them by autogenerated names like H0. In this case, we'll take any hypothesis that applies to and then solves the goal. *) match goal with H : _ |- _ => apply H; solve [auto] end. } } Qed. (* Put notations in a separate module or file so that importers can decide whether or not to use them. *) Module BarNotations. Infix "#" := bar (at level 40) : Z_scope. Notation "x '##'" := (bar x x) (at level 40) : Z_scope. End BarNotations.
Next: GNU Free Documentation License, Previous: Coq Style Guide, Up: Vericert Manual [Contents][Index]
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scheduling: | Scheduling | ||
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Previous: Index - Features, Up: Vericert Manual [Contents][Index]
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