A formally verified high-level synthesis (HLS) tool written in Coq, building on top of CompCert. This ensures the correctness of the C to Verilog translation according to our Verilog semantics and CompCert’s C semantics, removing the need to check the resulting hardware for behavioural correctness.
The project is currently a work in progress. Currently, the following C features are supported and have all been proven correct, providing a verified translation from C to Verilog:
- all int operations,
- non-recursive function calls,
- local arrays and pointers, and
- control-flow structures such as if-statements, for-loops, etc…
- OOPSLA ‘21
- Yann Herklotz, James D. Pollard, Nadesh Ramanathan, and John Wickerson. Formal Verification of High-Level Synthesis. In Proc. ACM Program. Lang. 5, OOPSLA, 2021. [ pdf ]
- LATTE ‘21
- Yann Herklotz and John Wickerson. High-level synthesis tools should be proven correct. In Workshop on Languages, Tools, and Techniques for Accelerator Design, 2021. [ pdf ]
Mailing lists #
For discussions, you can join the following mailing list: lists.sr.ht/~ymherklotz/vericert-discuss.